The limited flexibility of domain-specific accelerators renders them inefficient for the important class of streaming applications, such as in security and database analytics, whose optimal resource provisioning is workload dependent. Because provisioning hardware for the worst-case can be prohibitively expensive, these applications are often relegated to software execution. Field-Programmable Gate Arrays (FPGAs) are uniquely positioned to accelerate such input-dependent streaming applications, combining inherent programmability with hardware-class performance and efficiency. However, their adoption for customized accelerator deployments is hampered by the slow and rigid hardware-centric toolchains. At design time, RTL-based implementations offer limited customizability, while High-Level Synthesis (HLS) frameworks struggle to generate efficient solutions for input-dependent dataflows. Furthermore, at deployment time, design-space exploration (DSE) approaches rely on detailed simulations, infeasible for complex, real-world designs and workloads. Accelerating input-dependent streaming pipelines on FPGAs requires configurable implementations that expose a broad, performant design space, coupled with high-level performance abstractions to rapidly generate workload-specialized instantiations.
To address the design challenge, the first part of this dissertation identifies common input-dependent design patterns and presents a systematic methodology for representing them via the streaming paradigm in statically scheduled HLS. We showcase this methodology in the development of highly parameterizable HLS design templates for two primary application case studies. We introduce RapidScan, an HLS-based string matching library designed to enhance the customizability and portability of an existing RTL-based network intrusion detection accelerator. To demonstrate its cross-domain applicability, we use RapidScan to deploy RapidDetect, a 200 Gbps streaming log monitoring accelerator on a single FPGA-enabled server, achieving a 4x cost reduction compared to software-based solutions. We further explore the limitations in describing input-dependence in HLS by investigating packet routing within a database aggregation accelerator, compared against ReConnect, a novel RTL-native Network-on-Chip (NoC) generator. ReConnect harnesses the regularity in NoC structures to unlock a vast design space directly in RTL while reducing resource consumption by over 35% and seamlessly integrating with existing HLS workflows.
Leveraging the structure imparted by the streaming paradigm to input-dependent pipelines in HLS, in the second part of the thesis, we present RapidQ, a queuing-inspired performance modeling workflow for rapid workload-driven design-space exploration (DSE) at deployment time. RapidQ distills a workload’s input-dependent behavior into a workload model, capable of predicting performance across various design parameters, using a single functional simulation. RapidQ’s lightweight queueing simulator exercises this workload model to achieve a 7x speedup over state-of-the-art approaches and is over 100x faster than RTL simulation, without significant accuracy loss. Driven by this fast performance estimation, we designed an automated DSE flow that co-tunes module throughputs and buffer sizes, achieving up to 42% resource savings for real-world workloads.
By pairing HLS-powered, highly parameterized design templates with rapid queueing-based performance estimation, this thesis provides a scalable approach to designing and tuning input-dependent streaming pipelines, enabling hardware acceleration with customized deployments on FPGAs.