<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>Verilog-to-Routing (VTR) on Shashank Obla</title><link>https://shashankov.github.io/tags/verilog-to-routing-vtr/</link><description>Recent content in Verilog-to-Routing (VTR) on Shashank Obla</description><generator>Hugo</generator><language>en</language><lastBuildDate>Fri, 10 May 2024 00:00:00 +0000</lastBuildDate><atom:link href="https://shashankov.github.io/tags/verilog-to-routing-vtr/index.xml" rel="self" type="application/rss+xml"/><item><title>FPGA--: A From-Scratch FPGA Design and Tapeout</title><link>https://shashankov.github.io/projects/fpga-tapeout/</link><pubDate>Fri, 10 May 2024 00:00:00 +0000</pubDate><guid>https://shashankov.github.io/projects/fpga-tapeout/</guid><description>A custom 4x4 FPGA fabric featuring fracturable CLBs, configurable Switch and Connection Boxes, and JTAG-based programming, designed and taped out as part of CMU&amp;#39;s 18-725 class.</description></item></channel></rss>